Current microprocessors have a huge number of flip-flops (e.g., greater than 10,000). When testing or debugging the integrated circuit design, it is important to not only identify that a defect exists in the circuit, but the location and root cause of the defect. The use of scan design techniques to efficiently test and debug sequential circuits is a widely accepted industrial practice. In scan design, some or all flip-flops (or other sequential elements) in a circuit are linked into one or more scan chains. This permits data to be serially shifted into and out of these flip-flop chains, greatly enhancing controllability and observability of internal nodes in the design. If the data shifted into the scan chain comes out of the scan chain as predicted, it is determined that the flip-flops that make up the scan chain are not faulty.
After the circuit has been debugged and corrected, if necessary, the scan mechanism can be disabled, and the flip-flops may operate independently of one another.
In using scan design to test or debug a circuit, it is imperative that the scan chain itself not be defective. A defective scan chain will prevent the inputted data from being properly shifted through the chain and invalidate the testing of other parts of the logic.
Accordingly, what is needed is a design for sequential elements, such as flip-flops, which can be used to test or debug a circuit design via scanning, and in which any defects in the scan chain may be identified and precisely located.